Design of 8-bit Ripple Carry Adder Using Constant Delay Logic

This paper new design a Proposed Logic design targeting at full-custom high speed applications. The constant delay characteristic of this logic style regardless of the logic expression makes it suitable in implementing complicated logic expression such as addition. This feature enables performance advantage over static and dynamic, CD logic styles in a single cycle, multi-stage circuit block. Several design considerations including appropriate timing window width adjustment to reduce power consumption and maintain sufficient noise margin to ensure robust operations are discussed and analyzed. Using 50nm general purpose CMOS technology, the proposed logic style high performance compare to Static, dynamic & CD logic respectively. Post layout simulation results of 8-bit ripple carry adders conclude that Proposed logic faster than the compare to CD-based design Dynamic ,static based adders respectively. For ultra-high speed applications. This circuits design DSCH Tool, Microwind Tool.